test access port

The easy JTAG is introduced to control Test Access Port ( TAP ) by computer parallel port.

采用简易JTAG接口,通过计算机并口控制测试访问端口.

At last, it implements the programming state machine, which is to realize Firmware programming, in FPGA used VHDL. The state machine successfully produces the test access port scheduling which accords with JTAG protocol interface.

最后，用VHDL语言在FPGA内部实现了对固件编程的编程状态机，该状态机成功的产生了符合JTAG协议接口标准的测试端口时序，即固件编程时序。

The test access port and test logic architecture and protocol of 1149.4 and 1149.1 standards are analyzed, and behavior models for ABM and DBM are put forward.

文章分析了1149.4和1149.1标准的测试访问端口，以及测试逻辑结构和测试协议的异同，提出了模拟边界扫描单元ABM和数字边界扫描单元DBM的行为模型；

Investigation on Implementation of Standard Test Access Port and Boundary Scan Architecture at Board and System Levels

标准测试存取口与边界扫描结构在印制板级与系统级实现的探讨

Based on the jointed test action group ( JTAG) protocol, instructions and scan chain were introduced. With test access port ( TAP) module exchanging serial input with parallel output, register files and random access memory on chip were read or written in parallel.

在JTAG接口协议的基础上，增加指令和扫描链，同时通过测试访问端（TAP）控制把串行输入转换成并行输出，并行访问数字信号处理器的寄存器文件和片上存储器单元，实现嵌入式模拟器。

The easy JTAG is introduced to control Test Access Port ( TAP) by computer parallel port.

采用简易JTAG接口，通过计算机并口控制测试访问端口。